Manufacturing of semiconductor devices, in particular integrated circuits having multiple-layered structures with various metal and non-metal layers laminated on a semiconductor substrate, typically involves applications, of several metal layers onto a substrate or onto other previously deposited layers. These layers may have a complicated planer topology since these layers may constitute thousands of individual devices, which in combination form an integrated circuit or so-called “chip”. Modern chips may have metal or dielectric layers with thicknesses from tens of Angstroms to fractions of a micron.
It is understood that thin metallic filing used in integrated circuits of semiconductor devices function as conductors of electric current. Furthermore, it is known that densities of signal currents in metallic interconnections used in integrated circuits may reach extremely high values that generate such phenomena as electromigration associated with spatial transfer of mass of conductor films. Therefore the characteristics and properties of the deposited metal films (uniformity of film thickness, low electrical resistivity, etc.) determine performance characteristics and quality of the integrated circuit and of the semiconductor device as a whole.
In view of the above, thin metal films used in integrated circuits should satisfy very strict technical requirements relating to metal deposition processes, as well as to repeatability and controllability of the aforementioned processes.
A wide range of metals is utilized in tho microelectronic manufacturing industry for the formation of integrated circuits. These metals include, for example, nickel, tungsten, platinum, copper, cobalt, as well as alloys of electrically conductive compounds such as silicides, solders, etc. It is also known that coating films are applied onto substrates with the use of a variety of technological processes such chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating. Of these techniques, electroplating and electroless plating or deposition tend to be the most economical and most promising for improvement in characteristics of the deposited films. Therefore, electroplating and electroless plating techniques successfully replace other technologies.
Electroplating and electroless plating can be used for the deposition of continuous metal layers as well as patterned metal layers. One of the process sequences used by the microelectronic manufacturing industry to deposit metals onto semiconductor wafers is known to as “damascene” processing. In such processing, holes, commonly called “vias”, trenches and/or other recesses are formed on a workpiece and filled with a metal, such as copper. In the damascene process, the wafer, with vias and trenches etched in the dielectric material, is first provided with a metallic seed layer, which is used to conduct electrical current during a subsequent metal electroplating step. If a metal such as copper is used, the seed layer is disposed over a barrier layer material, such as Ti, TiN, etc. The seed layer is a very thin layer of metal, which can be applied using one or more processes. For example, the seed layer of metal can be laid down using physical vapor deposition or chemical vapor deposition processes to produce a layer with the thickness on the order of 1,000 Angstroms. The seed layer can advantageously be formed of copper, gold, nickel, palladium, or other metals. The seed layer is formed over a surface, which may contain vias, trenches, or other recessed device features.
A metal layer is then electroplated onto the seed layer in the form of a continuous layer. The continuous layer is plated to form an overlying layer, with the goal of providing a metal layer that fills the trenches and vias and extends a certain amount above these features. Such a continuous layer will typically have a thickness on the order of 5,000 to 15,000 Angstroms (0.5-1.5 microns).
After the continuous layer has been electroplated onto the semiconductor wafer, excess metal material present outside of the vias, trenches, or other recesses is removed. The metal is removed to provide a resulting pattern of metal layer in the semiconductor integrated circuit being formed. The excess plated material can be removed, for example, using chemical mechanical planarization. Chemical mechanical planarization is a processing step, which uses the combined action of chemical removal agents, or a chemical removal agents with an abrasive, which grinds and polishes the exposed metal surface to remove undesired parts of the metal layer applied in the electroplating step.
One drawback associated with copper deposition by electroplating is the fact that for very small features on microelectronic workpieces (sub 0.1 micron features), copper deposition by electroplating can lack conformity with the side walls of high aspect ratio vias and trenches, and can produce voids in the formed interconnects and plugs (vias). This is often due to the non-conformity of the copper seed layer deposited by PVD or CVD. As a result, the seed layer may not be thick enough to carry the current to the bottom of high aspect ratio features.
An alternate process for depositing copper onto a microelectronic workpiece is known as “electroless” plating which is the deposition of metals on a catalytic surface from a solution without an external source of current. For example, this process can be used as a preliminary step in preparing plastic articles for conventional electroplating. After cleaning and etching, the plastic surface is immersed in solutions that react to precipitate a catalytic metal in situ, palladium, for example. First the plastic is placed in an acidic stannous chloride solution, then into a solution of palladium chloride; palladium is reduced to its catalytic metallic state by the tin. Another way of producing a catalytic surface is to immerse the plastic article in a colloidal solution of palladium followed by immersion in an accelerator solution. The plastic article thus treated can now be plated with nickel or copper by the electroless method, which forms a conductive surface, which then can be plated with other metals by a conventional electroplating method.
As compared to electroplating, the electroless plating or deposition is a selective process, which can be realized with very thin seeds or without the use of seeds at all. Since electroless process is not associated with the use of an external electric current source, the electroless deposition results in more uniform coatings in view of the absence of discrete contacts. Electroless deposition can be realized with the use of simple and inexpensive equipment and with a high aspect ratio gap fill.
Given below are examples of existing methods and apparatuses for electroless deposition, specifically for use in the manufacture of semiconductor devices.
U.S. Pat. No. 5,500,315 issued in 1996 to J. Calvert, et al. discloses an electroless metal plating-catalyst system that overcomes many of the limitations of prior systems. In one aspect of the invention, the process comprises the steps of: providing a substrate with one or more chemical groups capable of ligating to an electroless deposition catalyst, at least a portion of the chemical groups being chemically bonded to the substrate; contacting the substrate with the electroless metal plating catalyst; and contacting the substrate with an electroless metal plating solution to form a metal deposit on the substrate. The chemical groups can be, for example, covalently bonded to the substrate. In another preferred aspect, the invention provides a process for selective electroless metallization, comprising steps of selectively modifying the reactivity of a substrate to an electroless metallization catalyst; contacting the substrate with the electroless metallization catalyst; and contacting the substrate with an electroless metallization solution to form a selective electroless deposit on the substrate. The substrate reactivity can be modified by selective treatment of catalyst ligating groups or precursors thereof on the substrate, for example by isomerization, photocleavage or other transformation of the ligating or precursor groups. Such-direct modification enables selective plating in a much more direct and convenient manner than prior selective plating techniques. Specifically, the aforementioned patent provides selective electroless deposition without the use of a photoresist or an adsorption type tin-containing plating catalyst.
U.S. Pat. No. 5,830,805 issued in 1998 to Y. Shacham-Diamand, et al. This patent discloses an electroless deposition apparatus and method of performing electroless deposition for processing a semiconductor wafer that use a closed processing chamber to subject the wafer to more than one processing fluid while retaining the wafer within the chamber. The invention is useful for manufacturing processes that include depositing, etching, cleaning, rinsing, and/or drying. The processing chamber used in the preferred embodiment of the apparatus of the above patent is an enclosed container capable of holding one or more semiconductor wafers. A distribution system introduces a first fluid into the chamber for processing the wafer and then removes the first fluid from the chamber after processing the wafer. The distribution system then introduces the next fluid into the chamber for processing the wafer and then removes the next fluid from the chamber after processing the wafer. This procedure continues until the manufacturing process finishes. The fluids used in the present invention depends on the process performed and may include fluids such as DI water, N2 for flushing, and electrolytic solutions comprising reducing agents, complexing agents, or pH adjusters.
The fluid enters the sealed processing chamber through an inlet, and exits the chamber through an outlet. As the fluid enters the processing chamber, the fluid is dispersed across the wafer in a uniform flow. A recirculation system moves the fluid through the processing chamber using a temperature control system, chemical concentration monitoring system, pump system, and a filtration system before re-circulating the fluid back through the processing chamber.
An essential part of any apparatus for treating wafer substrates in fluids, in particular of an apparatus for electroless deposition of a thin film onto a wafer substrate, is a wafer substrate holder or chuck which is used for holding the substrate during treatment at various stages of the process, such as coating, deposition, cleaning, rinsing, drying, etc.
One such substrate holder is described in U.S. Pat. No. 6,267,853 issued in 2001 to Y. Dordi, et al. This substrate holder has a pedestal that supports the substrate on the pedestal upper surface during processing. The pedestal actuator rotates the pedestal to spin the substrate and raises and lowers the pedestal relative to nozzles that supply the processing solutions. The substrate may be held in place on the pedestal by a plurality of clamps installed on the ends of radial arms attached to the upper end of the rotating pedestal. The clamps pivot with centrifugal force and engage the substrate preferably in the edge exclusion zone of the substrate. The entire substrate holder is located inside a bowl which can be filled with the process solution. For loading a substrate, the pedestal with the clamps is raised to a loading position with the clamps being open. After the substrate has been loaded, the pedestal is moved down to immerse the substrate into the solution. On its way down to the bowl, the clamps are released from the engagement with the clamp-opening ring and clamp the edges of the substrate. During its vertical movement from the pedestal actuator, the substrate can be stopped in an intermediate position approximately in the middle of the bowl height and so that the substrate is position between the upper and lower nozzles. As a result, the processing liquid can supplied to the upper and to the lower surface of the substrate simultaneously or selectively.
A main disadvantage of the substrate holder of U.S. Pat. No. 6,267,853 is that the backside surface always remains exposed to the action of the solution. In other words, the aforementioned device does not allow processing of one side of the substrate, while the other side is sealed against the process solution.
A substrate holder similar to the one described above is disclosed in International Patent Publication WO 02/063067 filed by Hiroshi Sato in 2002. The holder is provided with a platform which has on its periphery clamping jaws activated under the effect of centrifugal forces. The clamps are installed on vertical posts that provide a space between the platform and the bottom of the substrate for accommodating lower nozzles aimed at the backside periphery portion of the substrate. A group of other nozzles is arranged above the substrate. This holder is intended for holding the substrate during processing the substrate simultaneously from both sides. The main object of the aforementioned invention is to provide uniformity of treatment and to supply the processing solution to the edges and to the central parts of the substrate.
U.S. Pat. No. 4,747,608, issued in 1988 to Mitsuya Sato at al. describes a wafer chuck with radial clamps located under the edges of a substrate and which are moveable vertically and radially for clamping the edges of the substrate. For this purpose the clamps are provided with stopper projections that engage the substrate edge during a combined vertical and radial movement achieved due to the use of a complicated kinematic system. The chuck of this type is inapplicable for processing a substrate in liquids, especially for rotation with high speeds.
Thus it can be concluded that none of the aforementioned known substrate holders possesses universality and is capable of selectively providing treatment of substrates from both sides or only from the face side, while protecting the backside of the substrate from the effect of the process solution. Furthermore, some of the known holders have a complicated construction, and none of them utilize one and the same element for two functions, such as supporting the substrate and controlling operation of substrate clamping elements.